 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CY8CLED08 EZ-ColorTM HB LED Controller Features HB LED Controller Configurable dimmers support up to Eight independent LED channels 8- to 32- bits of resolution per channel Dynamic reconfiguration enables LED controller plus other features: CapSense(R), Battery Charging, and Motor Control Visual embedded design LED-Based drivers * Binning compensation * Temperature feedback * Optical feedback * DMX512 PrISM modulation technology Reduces radiated EMI Reduces low frequency blinking Powerful Harvard-architecture processor M8C processor speeds to 24 MHz 3.0 to 5.25 V operating voltage Operating voltages down to 1.0 V using on-chip switch mode pump (SMP) Industrial temperature range: -40 C to +85 C Flexible on-chip memory 16 K flash program storage 50,000 erase/write cycles 256 bytes static random access memory (SRAM) data storage In-system serial programming (ISSP) Partial flash updates Flexible protection modes EEPROM emulation in flash Advanced peripherals (PSoC(R) blocks) Eight digital PSoC blocks provide: * 8- to 32-bit timers, counters, and pulse-width modulator (PWMs) * Up to two full-duplex universal asynchronous receiver transmitter (UARTs) * Multiple serial peripheral interface (SPI) masters or slaves * Connectable to all general purpose I/O (GPIO) pins 12 Rail-to-Rail analog PSoC blocks provide: * Up to 14-bit ADCs * Up to 9-bit DACs * Programmable gain amplifiers (PGA) * Programmable filters and comparators Complex peripherals by combining blocks Programmable pin configurations 25 mA sink, 10 mA source on all GPIOs Pull-up, pull-down, high Z, strong, or open-drain drive modes on all GPIOs Up to 12 analog inputs on GPIOs Four 30 mA analog outputs on GPIOs Configurable interrupt on all GPIOs Complete development tools Free development software * PSoC DesignerTM Full featured, in-circuit emulator (ICE) and programmer Full speed emulation Complex breakpoint structure 128 KB trace memory Cypress Semiconductor Corporation Document Number: 001-12981 Rev. *J * 198 Champion Court * San Jose, CA 95134-1709 *408-943-2600 Revised July 8, 2011 CY8CLED08 Logic Block Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC CORE System Bus Global Digital Interconnect SRAM 256 Bytes Interrupt Controller Global Analog Interconnect Flash 16K Sleep and Watchdog SROM CPU Core (M8C) Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array ANALOG SYSTEM Analog Ref. Analog Block Array Analog Input Muxing Digital Clocks Multiply Accum. POR and LVD Decimator I 2C System Resets Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES Document Number: 001-12981 Rev. *J Page 2 of 52 CY8CLED08 Contents EZ-ColorTM Functional Overview..................................... 4 Target Applications ......................................................4 The PSoC Core ...........................................................4 The Digital System ......................................................4 The Analog System .....................................................5 Additional System Resources ......................................6 EZ-Color Device Characteristics .................................6 Getting Started ..................................................................6 Development Tools ...........................................................7 Designing with PSoC Designer .......................................8 Pin Information .................................................................9 Pinouts .........................................................................9 Register Reference .........................................................10 Register Conventions ................................................10 Register Mapping Tables ...........................................10 Electrical Specifications ................................................13 Absolute Maximum Ratings ......................................14 Operating Temperature ............................................14 DC Electrical Characteristics .....................................15 AC Electrical Characteristics .....................................31 Packaging Information ...................................................40 Packaging Dimensions ..............................................40 Thermal Impedances ................................................41 Capacitance on Crystal Pins ....................................41 Solder Reflow Peak Temperature .............................41 Development Tool Selection ..........................................42 Software Tools ...........................................................42 Hardware Tools .........................................................42 Evaluation Tools ........................................................42 Device Programmers .................................................43 Accessories (Emulation and Programming) ..............43 Ordering Information ......................................................44 Key Device Features .................................................44 Ordering Code Definitions ........................................44 Acronyms ........................................................................45 Reference Documents ....................................................45 Document Conventions .................................................46 Units of Measure .......................................................46 Numeric Conventions ................................................46 Glossary ..........................................................................46 Document History Page .................................................51 Sales, Solutions, and Legal Information ......................52 Products ....................................................................52 PSoC Solutions .........................................................52 Document Number: 001-12981 Rev. *J Page 3 of 52 CY8CLED08 1. EZ-ColorTM Functional Overview Cypress' EZ-Color family of devices offers the ideal control solution for high brightness LED applications requiring intelligent dimming control. EZ-Color devices combine the power and flexibility of Programmable System-on-Chip (PSoC(R)). Cypress' precise illumination signal modulation (PrISMTM) modulation technology provides lighting designers a fully customizable and integrated lighting solution platform. The EZ-Color family supports a range of independent LED channels from 4 channels at 32 bits of resolution each, up to 16 channels at 8 bits of resolution each. This enables lighting designers the flexibility to choose the LED array size and color quality. PSoC Designer software, with lighting specific drivers, can significantly cut development time and simplify implementation of fixed color points through temperature, optical, and LED binning compensation. EZ-Color's virtually limitless analog and digital customization enable simple integration of features in addition to intelligent lighting, such as battery charging, image stabilization, and motor control during the development process. These features, along with Cypress' best-in-class quality and design support, make EZ-Color the ideal choice for intelligent HB LED control applications. system resource), provide the flexibility to integrate almost any timing requirement into the EZ-Color device. EZ-Color GPIOs provide connection to the CPU, digital, and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. 1.3 The Digital System The digital system is composed of 8 digital blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. Figure 1-1. Digital System Block Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Digital Clocks From Core To System Bus To Analog System 1.1 Target Applications DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration LCD Backlight Large Signs General Lighting Architectural Lighting Camera/Cell Phone Flash Flashlights 8 8 Row Input Configuration Row 0 DBB00 DBB01 DCB02 4 DCB03 4 Row Output Configuration 8 8 Row Output Configuration Row 1 DBB10 DBB11 DCB12 4 DCB13 4 1.2 The PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable General Purpose I/O (GPIO). The M8C CPU core is a powerful processor with speeds up to 48 MHz, providing a four MIPS 8-bit Harvard-architecture microprocessor. The CPU uses an interrupt controller with 17 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and watchdog timers (WDT). Memory encompasses 16K of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2K of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The EZ-Color family incorporates flexible internal clock generators, including a 24 MHz internal main oscillator (IMO) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz internal low speed oscillator (ILO) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the external crystal oscillator (ECO) (32.768 kHz ECO) is available for use as a real time clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital peripheral configurations include the following: PrISM (8- to 32-bit) PWMs (8- to 32-bit) PWMs with dead band (8- to 32-bit) Counters (8- to 32-bit) Timers (8- to 32-bit) UART 8-bit with selectable parity (up to two) SPI slave and master (up to two) I2C slave and multi-master (one available as a system resource) Cyclical redundancy checker (CRC)/Generator (8- to 32-bit) IrDA (up to two) Generators (8- to 32-bit) Page 4 of 52 Document Number: 001-12981 Rev. *J CY8CLED08 The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also enable signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by EZ-Color device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled EZ-Color Device Characteristics. Figure 1-2. Analog System Block Diagram P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6] 1.4 The Analog System The analog system is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common EZ-Color analog functions (most available as user modules) are as follows: P2[3] P2[4] P2[2] P2[0] P2[1] Analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 4, with 16 selectable thresholds) DACs (up to 4, with 6- to 9-bit resolution) Multiplying DACs (up to 4, with 6- to 9-bit resolution) High current output drivers (four with 30 mA drive as a core resource) 1.3-V reference (as a system resource) DTMF Dialer Modulators Correlators Peak detectors Many other topologies possible Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap ASD20 ASC21 ASD22 ASC23 ACB00 ASC10 ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] Array Input Configuration Block Array ACB01 ASD11 ACB02 ASC12 ACB03 ASD13 Analog Reference Analog blocks are provided in columns of three, which includes one Continuous Time (CT) and two Switched Capacitor (SC) blocks, as shown in the figure below. M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-12981 Rev. *J Page 5 of 52 CY8CLED08 1.1 Additional System Resources System resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump (SMP), low-voltage detect (LVD), and power-on reset (POR). Statements describing the merits of each system resource are below. The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low-voltage detect (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR circuit eliminates the need for a system supervisor. An internal 1.3-V reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated SMP generates normal operating voltages from a single 1.2-V battery cell, providing a low cost boost converter. Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital blocks as clock dividers. Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. 1.2 EZ-Color Device Characteristics Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data sheet is shown in the highlighted row of the table. Table 1-1. EZ-Color Device Characteristics CapSense No Yes No No LED Channels Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital I/O Digital Rows SRAM Size Flash Size 4K 16K 16K 32K Part Number CY8CLED02 CY8CLED04 CY8CLED08 CY8CLED16 2 4 8 16 16 56 44 44 1 1 2 4 4 4 8 16 8 48 12 12 0 2 4 4 2 2 4 4 4 6 12 12 256 Bytes 1K 256 Bytes 2K 2. Getting Started The quickest way to understanding the EZ-Color silicon is by reading this data sheet and using the PSoC Designer integrated development environment (IDE). This data sheet is an overview of the EZ-Color integrated circuit and presents specific pin, register, and electrical specifications. For up-to-date ordering, packaging, and electrical specification information, see the latest device data sheets on the web at http://www.cypress.com. covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. Solutions Library Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Application Notes Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Technical Support Technical support - including a searchable Knowledge Base articles and technical forums - is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, Document Number: 001-12981 Rev. *J Page 6 of 52 CY8CLED08 3. Development Tools PSoC DesignerTM is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also lets you to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality in-circuit emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24 MHz) operation. Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration Extensive user module catalog Integrated source-code editor (C and assembly) Free C compiler with no size restrictions or time limits Built-in debugger In-circuit emulation Built-in support for communication interfaces: 2 Hardware and software I C slaves and masters Full-speed USB 2.0 Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this lets you to use more than 100 percent of PSoC's resources for an application. Document Number: 001-12981 Rev. *J Page 7 of 52 CY8CLED08 4. Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is: 1. Select user modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Organize and Connect Build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. Perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the "Generate Configuration Files" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides APIs with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. A complete code development environment lets you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger (accessed by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full-speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. It lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called "user modules." User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each eight bits of resolution. Using these parameters, you can establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All of the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. Document Number: 001-12981 Rev. *J Page 8 of 52 CY8CLED08 5. Pin Information 5.1 Pinouts 5.1.1 48-Pin Part Pinout QFN Table 5-1. 48-Pin Part Pinout (QFN)[1] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I I/O I I/O I/O I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Type Digital I/O I/O I/O I/O I/O I/O Power Analog I I Pin Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD P0[7] P0[5] Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input and column output. Active high external reset with internal pull down. Optional external clock input (EXTCLK). Crystal input (XTALin), I2C SCL, ISSP-SCLK[1]. Ground connection. Crystal Output (XTALout), I2C SDA, ISSP-SDATA[1]. I2C serial clock (SCL). I2C serial data (SDA). Switch mode pump (SMP) connection to external components required. Description Direct switched capacitor block input. Direct switched capacitor block input. Figure 5-1. 48-Pin Device Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VRef 36 35 34 33 32 31 30 29 28 27 26 25 P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] Notes 1. These are the ISSP pins, which are not High Z at POR. 2. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. Document Number: 001-12981 Rev. *J I2C SCL, XTALin, P1[1] Vss I2C SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] P1[6] P5[0] P5[2] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] 13 14 15 16 17 18 19 20 21 22 23 24 A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 P2[5] P2[7] P0[1], A, I P0[3], A, IO P0[5], A, IO P0[7], A, I QFN (Top View) Page 9 of 52 CY8CLED08 Table 5-1. 48-Pin Part Pinout (QFN)[1] 45 46 47 48 I/O I/O I/O I/O I/O I P0[3] P0[1] P2[7] P2[5] Analog column mux input and column output. Analog column mux input. LEGEND: A = Analog, I = Input, and O = Output. 6. Register Reference This section lists the registers of the CY8CLED08 EZ-Color device. 6.1 Register Conventions The register conventions specific to this section are listed in the following table. Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific 6.2 Register Mapping Tables The device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks, Bank 0 and Bank 1. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set to 1, the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and should not be accessed. Table 6-1. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 Access I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 D6 D7 D8 D9 DA DB DC DD DE RW # RW # RW RW RW RW Blank fields are Reserved and should not be accessed. # Access is bit specific. Document Number: 001-12981 Rev. *J Page 10 of 52 CY8CLED08 Table 6-1. Register Map Bank 0 Table: User Space (continued) Name DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 DBB10DR0 DBB10DR1 DBB10DR2 DBB10CR0 DBB11DR0 DBB11DR1 DBB11DR2 DBB11CR0 DCB12DR0 DCB12DR1 DCB12DR2 DCB12CR0 DCB13DR0 DCB13DR1 DCB13DR2 DCB13CR0 Addr (0,Hex) 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Access # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # Name AMX_IN Addr (0,Hex) 5F 60 61 62 Access RW Name ASC23CR3 Addr (0,Hex) 9F A0 A1 A2 Access RW Name INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1 ACC_DR0 ACC_DR3 ACC_DR2 Addr (0,Hex) DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 Access RW RW RC W RC RC RW RW W W R R RW RW RW RW ARF_CR CMP_CR0 ASY_CR CMP_CR1 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F RW # # RW A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 ACB03CR2 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 F7 F8 F9 FA FB FC FD FE FF RL # # Blank fields are Reserved and should not be accessed. # Access is bit specific. Table 6-2. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Add (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A Blank fields are Reserved and should not be accessed. Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU Name Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA RW RW RW RW Access # Access is bit specific. Document Number: 001-12981 Rev. *J Page 11 of 52 CY8CLED08 Table 6-2. Register Map Bank 1 Table: Configuration Space (continued) Name Add (1,Hex) 1B 1C 1D 1E 1F DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU DCB03FN DCB03IN DCB03OU DBB10FN DBB10IN DBB10OU DBB11FN DBB11IN DBB11OU DCB12FN DCB12IN DCB12OU DCB13FN DCB13IN DCB13OU 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 ACB03CR2 RW RW RW RW RW RW RW RW RW AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 RW RW RW CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 Access Name Addr (1,Hex) 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RW RW RW RW RW RW RW RW Access Name ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr (1,Hex) 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 RW RW RW RW RW RW RW CPU_F IMO_TR ILO_TR BDG_TR ECO_TR Access RW RW RW RW RW OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP Name Addr (1,Hex) DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RL W W RW W RW RW RW RW RW RW RW R Access Blank fields are Reserved and should not be accessed. Document Number: 001-12981 Rev. *J Page 12 of 52 CY8CLED08 7. Electrical Specifications This section presents the DC and AC electrical specifications of the CY8CLED08 EZ-Color device. For the most up to date electrical specifications, confirm that you have the most recent datasheet by going to the web at http://www.cypress.com. Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40 C TA 70 C and TJ 82 C. Figure 7-1. Voltage vs. CPU Frequency 5.25 4.75 Vdd Voltage 3.00 93 kHz CPU Frequency lid ng Va rati n pe io O eg R 12 MHz 24 MHz Document Number: 001-12981 Rev. *J Page 13 of 52 CY8CLED08 7.1 Absolute Maximum Ratings Table 7-1. Absolute Maximum Ratings Symbol TSTG Description Storage temperature Min -55 Typ 25 Max +100 Units C Notes Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25 C 25 C. Extended duration storage temperatures above 65 C will degrade reliability. TBAKETEMP Bake temperature - 125 TBAKETIME Bake Time TA VDD VIO VIOZ IMIO IMAIO ESD LU Ambient temperature with power applied Supply voltage on VDD relative to Vss DC input voltage DC voltage applied to tri-state Maximum current into any port pin Maximum current into any port pin configured as analog driver Electrostatic discharge voltage Latch up current See package label -40 -0.5 Vss- 0.5 Vss - 0.5 -25 -50 2000 - - See package label 72 C Hours - - - - - - - - +85 +6.0 VDD + 0.5 VDD + 0.5 +50 +50 - 200 C V V V mA mA V mA Human Body Model ESD. 7.2 Operating Temperature Table 7-2. Operating Temperature Symbol TA TJ Description Ambient temperature Junction temperature Min -40 -40 Typ - - Max +85 +100 Units C C Notes The temperature rise from ambient to junction is package specific. See Thermal Impedances on page 41. The user must limit the power consumption to comply with this requirement. Document Number: 001-12981 Rev. *J Page 14 of 52 CY8CLED08 7.3 DC Electrical Characteristics 7.3.1 DC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 C and are for design guidance only. Table 7-3. DC Chip-Level Specifications Symbol VDD IDD Description Supply voltage Supply current Min 3.00 - Typ - 5 Max 5.25 8 Units V mA Notes Conditions are VDD = 5.0 V, TA = 25 C, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are VDD = 3.3 V, TA = 25 C, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are with internal slow speed oscillator, VDD = 3.3 V, -40 C TA 55 C. Conditions are with internal slow speed oscillator, VDD = 3.3 V, 55 C < TA 85 C. Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. VDD = 3.3 V, -40 C TA 55 C. Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. VDD = 3.3 V, 55 C < TA 85 C. Trimmed for appropriate VDD. Trimmed for appropriate VDD. IDD3 Supply current - 3.3 6.0 mA ISB Sleep (mode) current with POR, LVD, sleep timer, and WDT.[3] Sleep (mode) current with POR, LVD, sleep timer, and WDT at high temperature.[3] Sleep (mode) current with POR, LVD, sleep timer, WDT, and external crystal.[3] - 3 6.5 A A A ISBH - 4 25 ISBXTL - 4 7.5 ISBXTLH Sleep (mode) current with POR, LVD, sleep timer, WDT, and external crystal at high temperature.[3] Reference voltage (Bandgap) for Silicon A [4] Reference voltage (Bandgap) for Silicon B [4] - 5 26 A VREF VREF 1.275 1.280 1.300 1.300 1.325 1.320 V V Notes 3. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions enabled. 4. Refer to the "Ordering Information" on page 44. Document Number: 001-12981 Rev. *J Page 15 of 52 CY8CLED08 7.3.2 DC GPIO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 C and are for design guidance only. Table 7-4. DC GPIO Specifications Symbol RPU RPD VOH Description Pull-up resistor Pull-down resistor High output level Min 4 4 VDD - 1.0 Typ 5.6 5.6 - Max 8 8 - Units k k V Notes VOL Low output level - - 0.75 V IOH High level source current 10 - - mA IOL VIL VIH VH IIL CIN COUT Low level sink current Input low level Input high level Input hysterisis Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output 25 - 2.1 - - - - - - - 60 1 3.5 3.5 - 0.8 - - 10 10 mA V V mV nA pF pF IOH = 10 mA, VDD = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). VOH = VDD-1.0 V. See the limitations of the total current in the Note for VOH. VOL = 0.75 V. See the limitations of the total current in the Note for VOL. VDD = 3.0 to 5.25. VDD = 3.0 to 5.25. Gross tested to 1 A. Package and pin dependent. Temp = 25 C. Package and pin dependent. Temp = 25 C. 7.3.3 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at to 5 V and 3.3 V at 25 C and are for design guidance only. The operational amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25 C and are for design guidance only. Table 1. 5-V DC Operational Amplifier Specifications Symbol VOSOA Description Input offset voltage (absolute value) Power = low, opamp bias = low Power = low, opamp bias = high Power = medium, opamp bias = low Power = medium, opamp bias = high Power = high, opamp bias = low Power = high, opamp bias = high Input leakage current (port 0 analog pins) Input capacitance (port 0 analog pins) Min - - - - - - - - - Typ 1.6 1.6 1.6 1.6 1.6 1.6 4 20 4.5 Max 10 10 10 10 10 10 20 - 9.5 Units mV mV mV mV mV mV V/C pA pF Gross tested to 1 A. Package and pin dependent. Temp = 25 C Notes TCVOSOA Average input offset voltage drift IEBOA CINOA Document Number: 001-12981 Rev. *J Page 16 of 52 CY8CLED08 Table 1. 5-V DC Operational Amplifier Specifications Symbol VCMOA Description Common mode voltage range Min 0 Typ - Max VDD Units V Notes The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Common mode voltage range (high power or high opamp bias) CMRROA Common mode rejection ratio Power = low, opamp bias = high Power = medium, opamp bias = high Power = high, opamp bias = high GOLOA Open loop gain Power = low, opamp bias = high Power = medium, opamp bias = high Power = high, opamp bias = high High output voltage swing (internal signals) Power = low, opamp bias = high Power = medium, opamp bias = high Power = high, opamp bias = high 0.5 - VDD - 0.5 - - - - - - V Specification is applicable at both High and Low opamp bias. 60 60 60 60 60 80 - - - - - - dB dB dB dB dB dB Specification is applicable at High opamp bias. For Low opamp bias mode, minimum is 60dB. VOHIGHO A VDD - 0.2 VDD - 0.2 VDD - 0.5 - - - - - - - - - V V V VOLOWOA Low output voltage swing (internal signals) Power = low, opamp bias = high Power = medium, opamp bias = high Power = high, opamp bias = high ISOA Supply current (including associated AGND buffer) Power = low, opamp bias = low Power = low, opamp bias = high Power = medium, opamp bias = low Power = medium, opamp bias = high Power = high, opamp bias = low Power = high, opamp bias = high Supply voltage rejection ratio - - - 0.2 0.2 0.5 V V V - - - - - - 60 150 300 600 1200 2400 4600 - 200 400 800 1600 3200 6400 - A A A A A A dB Vss VIN (VDD - 2.25) or (VDD - 1.25 V) VIN VDD. PSRROA Table 2. 3.3-V DC Operational Amplifier Specifications Symbol VOSOA Description Input offset voltage (absolute value) Power = low, opamp bias = low Power = low, opamp bias = high Power = medium, opamp bias = low Power = medium, opamp bias = high Power = high, opamp bias = low Power = high, opamp bias = high Input leakage current (port 0 analog pins) Input capacitance (port 0 analog pins) Common mode voltage range Min - - - - - - - - - 0.2 Typ 1.4 1.4 1.4 1.4 1.4 - 7 20 4.5 - Max 10 10 10 10 10 - 40 - 9.5 VDD - 0.2 Unit mV mV mV mV mV mV V/C pA pF V Gross tested to 1A. Package and pin dependent. Temp = 25 C. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Notes Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation. TCVOSOA Average input offset voltage drift IEBOA CINOA VCMOA Document Number: 001-12981 Rev. *J Page 17 of 52 CY8CLED08 Table 2. 3.3-V DC Operational Amplifier Specifications (continued) Symbol CMRROA Description Common mode rejection ratio Power = low, opamp bias = low Power = medium, opamp bias = low Power = high, opamp bias = low Open loop gain Power = low, opamp bias = low Power = medium, opamp bias = low Power = high, opamp bias = low Min 50 50 50 60 60 80 VDD - 0.2 VDD - 0.2 VDD - 0.2 - - - Typ - - - - - - - - - Max - - - - - - - - - Unit dB dB dB dB dB dB V V V Notes Specification is applicable at Low opamp bias. For High bias mode (except High Power, High opamp bias), minimum is 60 dB. Specification is applicable at Low opamp bias. For High opamp bias mode (except High Power, High opamp bias), minimum is 60 dB. Power = high, opamp bias = high setting is not allowed for 3.3 V VDD operation. GOLOA VOHIGHOA High output voltage swing (internal signals) Power = low, opamp bias = low Power = medium, opamp bias = low Power = high, opamp bias = low VOLOWOA Low output voltage swing (internal signals) Power = low, opamp bias = low Power = medium, opamp bias = low Power = high, opamp bias = low ISOA Supply current (including associated AGND buffer) Power = low, opamp bias = low Power = low, opamp bias = high Power = medium, opamp bias = low Power = medium, opamp bias = high Power = high, opamp bias = low Power = high, opamp bias = high Supply voltage rejection ratio - - - 0.2 0.2 0.2 V V V Power = high, opamp bias = high setting is not allowed for 3.3 V VDD operation. - - - - - - 50 150 300 600 1200 2400 - 80 200 400 800 1600 3200 - - A A A A A A dB Power = high, opamp bias = high setting is not allowed for 3.3 V VDD operation. PSRROA VSS VIN (VDD - 2.25) or (VDD - 1.25 V) VIN VDD. 7.3.4 DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, 3.0 V to 3.6 V and -40 C TA 85 C, or 2.4 V to 3.0 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V at 25 C and are for design guidance only. Table 7-5. DC Low Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Min 0.2 - - Typ - 10 2.5 Max VDD - 1 40 30 Units V A mV Notes Document Number: 001-12981 Rev. *J Page 18 of 52 CY8CLED08 7.3.5 DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 C and are for design guidance only. Table 3. 5-V DC Analog Output Buffer Specifications Description Min Input offset voltage (absolute value) - Power = low, opamp bias = low - Power = low, opamp bias = high - Power = high, opamp bias = low - Power = high, opamp bias = high - TCVOSOB Average input offset voltage drift Common-mode input voltage 0.5 VCMOB range ROUTOB Output resistance Power = low - Power = high - VOHIGHOB High output voltage swing (Load = 32 ohms to VDD/2) Power = low 0.5 x VDD + 1.3 Power = high 0.5 x VDD + 1.3 VOLOWOB Low output voltage swing (Load = 32 ohms to VDD/2) Power = low - Power = high - Supply current including opamp ISOB bias cell (no load) Power = low - Power = high - PSRROB Supply voltage rejection ratio 60 Maximum output current - IOMAX Load capacitance - CL Symbol VOSOB Typ 3 3 3 3 5 - Max 19 19 19 19 30 VDD - 1.0 - - Unit mV mV mV mV V/C V Notes 1 1 W W - - - - V V - - 0.5 x VDD - 1.3 0.5 x VDD - 1.3 5.1 8.8 - - 200 V V 1.1 2.6 64 40 - mA mA dB mA pF This specification applies to the external circuit driven by the analog output buffer. Document Number: 001-12981 Rev. *J Page 19 of 52 CY8CLED08 Table 4. 3.3-V DC Analog Output Buffer Specifications Symbol VOSOB Description Min Input offset voltage (absolute value) - Power = low, opamp bias = low - Power = low, opamp bias = high - Power = high, opamp bias = low - Power = high, opamp bias = high TCVOSOB Average input offset voltage drift Power = low, opamp bias = low - Power = low, opamp bias = high - Power = high, opamp bias = low - Power = high, opamp bias = high - Common-mode input voltage 0.5 VCMOB range Output resistance ROUTOB Power = low - Power = high - VOHIGHOB High output voltage swing (load = 32 ohms to VDD/2) Power = low 0.5 x VDD + 1.0 Power = high 0.5 x VDD + 1.0 VOLOWOB Low output voltage swing (load = 32 ohms to VDD/2) Power = low - Power = high - Supply current including opamp ISOB bias cell (no load) Power = low - Power = high - PSRROB Supply voltage rejection ratio 60 Load capacitance - CL Typ 3.2 3.2 6 6 Max 20 20 25 25 Unit mV mV mV mV Notes High power setting is not recommended. 9 9 12 12 - 55 55 70 70 VDD - 1.0 - - V/C V/C V/C V/C V High power setting is not recommended. 1 1 W W - - - - V V - - 0.5 x VDD - 1.0 0.5 x VDD - 1.0 2 4.3 - 200 V V 0.8 2.0 64 - mA mA dB pF This specification applies to the external circuit driven by the analog output buffer. Document Number: 001-12981 Rev. *J Page 20 of 52 CY8CLED08 7.3.6 DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at to 5 V and 3.3 V at 25 C and are for design guidance only. Table 7-6. DC Switch Mode Pump (SMP) Specifications Symbol VPUMP 5 V Description 5 V output voltage Min 4.75 Typ 5.0 Max 5.25 Units V Notes Configured as in Note 5. Average, neglecting ripple. SMP trip voltage is set to 5.0 V. Configured as in Note 5. Average, neglecting ripple. SMP trip voltage is set to 3.25 V. Configured as in Note 5. SMP trip voltage is set to 3.25 V. SMP trip voltage is set to 5.0 V. Configured as in Note 5. SMP trip voltage is set to 5.0 V. Configured as in Note 5. SMP trip voltage is set to 3.25 V. Configured as in Note 5. Configured as in Note 5. VO is the "VDD Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 7-8 on page 29. Configured as in Note 5. VO is the "VDD Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 7-8 on page 29. Configured as in Note 5. Load is 5 mA. Configured as in Note 5. Load is 5 mA. SMP trip voltage is set to 3.25 V. VPUMP 3 V 3 V output voltage 3.00 3.25 3.60 V IPUMP VBAT5V VBAT3V VBATSTART VPUMP_Line Available output current VBAT = 1.5 V, VPUMP = 3.25 V VBAT = 1.8 V, VPUMP = 5.0 V Input voltage range from battery Input voltage range from battery Minimum input voltage from battery to start pump Line regulation (over VBAT range) 8 5 1.8 1.0 1.1 - - - - - - 5 - - 5.0 3.3 - - mA mA V V V %VO VPUMP_Load Load regulation - 5 - %VO VPUMP_Ripple Output voltage ripple (depends on capacitor/load) Efficiency E3 - 35 100 50 - - mVpp % FPUMP DCPUMP Switching frequency Switching duty cycle - - 1.3 50 - - MHz % Note 5. L1 = 2 H inductor, C1 = 10 F capacitor, D1 = Schottky diode. Document Number: 001-12981 Rev. *J Page 21 of 52 CY8CLED08 Figure 7-2. Basic Switch Mode Pump Circuit D1 Vdd VPUMP L1 VBAT C1 SMP + Battery EZ-Color Vss 7.0.1 DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 5. 5-V DC Analog Reference Specifications Referenc e ARF_CR [5:3] Reference Power Settings RefPower = high Opamp bias = high Symbol VREFHI VAGND VREFLO RefPower = high Opamp bias = low 0b000 VREFHI VAGND VREFLO RefPower = medium Opamp bias = high VREFHI VAGND VREFLO RefPower = medium Opamp bias = low VREFHI VAGND VREFLO Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap Min VDD/2 + 1.228 VDD/2 - 0.078 VDD/2 - 1.336 VDD/2 + 1.224 VDD/2 - 0.056 VDD/2 - 1.338 VDD/2 + 1.226 VDD/2 - 0.057 VDD/2 - 1.337 VDD/2 + 1.226 VDD/2 - 0.047 VDD/2 - 1.338 Typ VDD/2 + 1.290 VDD/2 - 0.007 VDD/2 - 1.295 VDD/2 + 1.293 VDD/2 - 0.005 VDD/2 - 1.298 VDD/2 + 1.293 VDD/2 - 0.006 VDD/2 - 1.298 VDD/2 + 1.294 VDD/2 - 0.004 VDD/2 - 1.299 Max VDD/2 + 1.352 VDD/2 + 0.063 VDD/2 - 1.250 VDD/2 + 1.356 VDD/2 + 0.043 VDD/2 - 1.255 VDD/2 + 1.356 VDD/2 + 0.044 VDD/2 - 1.256 VDD/2 + 1.359 VDD/2 + 0.035 VDD/2 - 1.258 Unit V V V V V V V V V V V V Document Number: 001-12981 Rev. *J Page 22 of 52 CY8CLED08 Table 5. 5-V DC Analog Reference Specifications (continued) Referenc e ARF_CR [5:3] Reference Power Settings RefPower = high Opamp bias = high Symbol VREFHI Reference Ref High Description P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] - P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] - P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] - P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] - P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS Min P2[4] + P2[6] - 0.085 P2[4] P2[4] - P2[6] - 0.022 P2[4] + P2[6] - 0.077 P2[4] P2[4] - P2[6] - 0.022 P2[4] + P2[6] - 0.070 P2[4] P2[4] - P2[6] - 0.022 P2[4] + P2[6] - 0.070 P2[4] P2[4] - P2[6] - 0.022 VDD - 0.037 VDD/2 - 0.061 VSS VDD - 0.039 VDD/2 - 0.049 VSS VDD - 0.037 VDD/2 - 0.054 VSS VDD - 0.042 VDD/2 - 0.046 VSS Typ Max Unit V P2[4] + P2[6] - P2[4] + P2[6] + 0.016 0.044 P2[4] P2[4] VAGND VREFLO AGND Ref Low - V P2[4] - P2[6] + P2[4] - P2[6] + 0.010 0.055 P2[4] + P2[6] - P2[4] + P2[6] + 0.010 0.051 P2[4] P2[4] RefPower = high Opamp bias = low VREFHI Ref High V VAGND VREFLO 0b001 AGND Ref Low - V P2[4] - P2[6] + P2[4] - P2[6] + 0.005 0.039 P2[4] + P2[6] - P2[4] + P2[6] + 0.010 0.050 P2[4] P2[4] RefPower = medium Opamp bias = high VREFHI Ref High V VAGND VREFLO AGND Ref Low - V P2[4] - P2[6] + P2[4] - P2[6] + 0.005 0.039 P2[4] + P2[6] - P2[4] + P2[6] + 0.007 0.054 P2[4] P2[4] RefPower = medium Opamp bias = low VREFHI Ref High V VAGND VREFLO AGND Ref Low - V P2[4] - P2[6] + P2[4] - P2[6] + 0.002 0.032 VDD - 0.009 VDD/2 - 0.006 VSS + 0.007 VDD - 0.006 VDD/2 - 0.005 VSS + 0.005 VDD - 0.007 VDD/2 - 0.005 VSS + 0.006 VDD - 0.005 VDD/2 - 0.004 VSS + 0.004 VDD VDD/2 + 0.047 VSS + 0.028 VDD VDD/2 + 0.036 VSS + 0.019 VDD VDD/2 + 0.041 VSS + 0.024 VDD VDD/2 + 0.034 VSS + 0.017 RefPower = high Opamp bias = high VREFHI VAGND VREFLO VREFHI VAGND VREFLO VREFHI VAGND VREFLO VREFHI VAGND VREFLO Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low V V V V V V V V V V V V RefPower = high Opamp bias = low 0b010 RefPower = medium Opamp bias = high RefPower = medium Opamp bias = low Document Number: 001-12981 Rev. *J Page 23 of 52 CY8CLED08 Table 5. 5-V DC Analog Reference Specifications (continued) Referenc e ARF_CR [5:3] Reference Power Settings RefPower = high Opamp bias = high Symbol VREFHI VAGND VREFLO RefPower = high Opamp bias = low 0b011 VREFHI VAGND VREFLO RefPower = medium Opamp bias = high VREFHI VAGND VREFLO RefPower = medium Opamp bias = low VREFHI VAGND VREFLO RefPower = high Opamp bias = high VREFHI Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High Description 3 x Bandgap 2 x Bandgap Bandgap 3 x Bandgap 2 x Bandgap Bandgap 3 x Bandgap 2 x Bandgap Bandgap 3 x Bandgap 2 x Bandgap Bandgap 2 x Bandgap + P2[6] (P2[6] = 1.3 V) 2 x Bandgap 2 x Bandgap - P2[6] (P2[6] = 1.3 V) 2 x Bandgap + P2[6] (P2[6] = 1.3 V) 2 x Bandgap 2 x Bandgap - P2[6] (P2[6] = 1.3 V) 2 x Bandgap + P2[6] (P2[6] = 1.3 V) 2 x Bandgap 2 x Bandgap - P2[6] (P2[6] = 1.3 V) 2 x Bandgap + P2[6] (P2[6] = 1.3 V) 2 x Bandgap 2 x Bandgap - P2[6] (P2[6] = 1.3 V) Min 3.788 2.500 1.257 3.792 2.518 1.256 3.795 2.516 1.256 3.792 2.522 1.255 2.495 - P2[6] Typ 3.891 2.604 1.306 3.893 2.602 1.302 3.894 2.603 1.303 3.895 2.602 1.301 2.586 - P2[6] Max 3.986 3.699 1.359 3.982 2.692 1.354 3.993 2.698 1.353 3.986 2.685 1.350 2.657 - P2[6] Unit V V V V V V V V V V V V V VAGND VREFLO AGND Ref Low 2.502 2.531 - P2[6] 2.604 2.611 - P2[6] 2.719 2.681 - P2[6] V V RefPower = high Opamp bias = low VREFHI Ref High 2.500 - P2[6] 2.591 - P2[6] 2.662 - P2[6] V VAGND VREFLO 0b100 AGND Ref Low 2.519 2.530 - P2[6] 2.602 2.605 - P2[6] 2.693 2.666 - P2[6] V V RefPower = medium Opamp bias = high VREFHI Ref High 2.503 - P2[6] 2.592 - P2[6] 2.662 - P2[6] V VAGND VREFLO AGND Ref Low 2.517 2.529 - P2[6] 2.603 2.606 - P2[6] 2.698 2.665 - P2[6] V V RefPower = medium Opamp bias = low VREFHI Ref High 2.505 - P2[6] 2.594 - P2[6] 2.665 - P2[6] V VAGND VREFLO AGND Ref Low 2.525 2.528 - P2[6] 2.602 2.603 - P2[6] 2.685 2.661 - P2[6] V V Document Number: 001-12981 Rev. *J Page 24 of 52 CY8CLED08 Table 5. 5-V DC Analog Reference Specifications (continued) Referenc e ARF_CR [5:3] Reference Power Settings RefPower = high Opamp bias = high Symbol VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO 0b101 RefPower = medium Opamp bias = high VREFHI VAGND VREFLO RefPower = medium Opamp bias = low VREFHI VAGND VREFLO RefPower = high Opamp bias = high VREFHI VAGND VREFLO RefPower = high Opamp bias = low 0b110 VREFHI VAGND VREFLO RefPower = medium Opamp bias = high VREFHI VAGND VREFLO RefPower = medium Opamp bias = low VREFHI VAGND VREFLO RefPower = high Opamp bias = high VREFHI VAGND VREFLO RefPower = high Opamp bias = low 0b111 VREFHI VAGND VREFLO RefPower = medium Opamp bias = high VREFHI VAGND VREFLO RefPower = medium Opamp bias = low VREFHI VAGND VREFLO Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) 2 x Bandgap Bandgap VSS 2 x Bandgap Bandgap VSS 2 x Bandgap Bandgap VSS 2 x Bandgap Bandgap VSS 3.2 x Bandgap 1.6 x Bandgap VSS 3.2 x Bandgap 1.6 x Bandgap VSS 3.2 x Bandgap 1.6 x Bandgap VSS 3.2 x Bandgap 1.6 x Bandgap VSS Min P2[4] + 1.222 P2[4] P2[4] - 1.331 P2[4] + 1.226 P2[4] P2[4] - 1.331 P2[4] + 1.227 P2[4] P2[4] - 1.331 P2[4] + 1.228 P2[4] P2[4] - 1.332 2.535 1.227 VSS 2.530 1.244 VSS 2.532 1.239 VSS 2.528 1.249 VSS 4.041 1.998 VSS 4.047 2.012 VSS 4.049 2.008 VSS 4.047 2.016 VSS Typ P2[4] + 1.290 P2[4] P2[4] - 1.295 P2[4] + 1.293 P2[4] P2[4] - 1.298 P2[4] + 1.294 P2[4] P2[4] - 1.298 P2[4] + 1.295 P2[4] P2[4] - 1.299 2.598 1.305 VSS + 0.009 2.598 1.303 VSS + 0.005 2.598 1.304 VSS + 0.006 2.598 1.302 VSS + 0.004 4.155 2.083 VSS + 0.010 4.153 2.082 VSS + 0.006 4.154 2.083 VSS + 0.006 4.154 2.081 VSS + 0.004 Max P2[4] + 1.343 P2[4] P2[4] - 1.254 P2[4] + 1.347 P2[4] P2[4] - 1.259 P2[4] + 1.347 P2[4] P2[4] - 1.259 P2[4] + 1.349 P2[4] P2[4] - 1.260 2.644 1.398 VSS + 0.038 2.643 1.370 VSS + 0.024 2.644 1.380 VSS + 0.026 2.645 1.362 VSS + 0.018 4.234 2.183 VSS + 0.038 4.236 2.157 VSS + 0.024 4.238 2.165 VSS + 0.026 4.238 2.150 VSS + 0.018 Unit V - V V - V V - V V - V V V V V V V V V V V V V V V V V V V V V V V V V Document Number: 001-12981 Rev. *J Page 25 of 52 CY8CLED08 Table 6. 3.3-V DC Analog Reference Specifications Reference ARF_CR [5:3] Reference Power Settings Symbol Reference VREFHI RefPower = high Opamp bias = high VAGND VREFLO VREFHI RefPower = high Opamp bias = low 0b000 RefPower = medium Opamp bias = high VAGND VREFLO VREFHI VAGND VREFLO VREFHI RefPower = medium Opamp bias = low VAGND VREFLO VREFHI RefPower = high Opamp bias = high VAGND VREFLO VREFHI RefPower = high Opamp bias = low VAGND VREFLO 0b001 VREFHI RefPower = medium Opamp bias = high VAGND VREFLO VREFHI RefPower = medium Opamp bias = low VAGND VREFLO Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4] - P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4] - P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4]-P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4]-P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) Min VDD/2 + 1.225 VDD/2 - 0.067 VDD/2 - 1.35 VDD/2 + 1.218 VDD/2 - 0.038 VDD/2 - 1.329 VDD/2 + 1.221 VDD/2 - 0.050 VDD/2 - 1.331 VDD/2 + 1.226 VDD/2 - 0.028 VDD/2 - 1.329 P2[4] + P2[6] - 0.098 P2[4] P2[4] - P2[6] - 0.055 P2[4] + P2[6] - 0.082 P2[4] P2[4] - P2[6] - 0.037 P2[4] + P2[6] - 0.079 P2[4] P2[4] - P2[6] - 0.038 P2[4] + P2[6] - 0.080 P2[4] P2[4] - P2[6] - 0.032 Typ Max Unit V V V V V V V V V V V V V - V V - V V - V V - V VDD/2 + 1.292 VDD/2 + 1.361 VDD/2 - 0.002 VDD/2 + 0.063 VDD/2 - 1.293 VDD/2 - 1.210 VDD/2 + 1.294 VDD/2 + 1.370 VDD/2 - 0.001 VDD/2 + 0.035 VDD/2 - 1.296 VDD/2 - 1.259 VDD/2 + 1.294 VDD/2 + 1.366 VDD/2 - 0.002 VDD/2 + 0.046 VDD/2 - 1.296 VDD/2 - 1.260 VDD/2 + 1.295 VDD/2 + 1.365 VDD/2 - 0.001 VDD/2 + 0.025 VDD/2 - 1.297 VDD/2 - 1.262 P2[4] + P2[6] - 0.018 P2[4] P2[4] - P2[6] + 0.013 P2[4] + P2[6] - 0.011 P2[4] P2[4] - P2[6] + 0.006 P2[4] + P2[6] - 0.012 P2[4] P2[4] - P2[6] + 0.006 P2[4] + P2[6] - 0.008 P2[4] P2[4] - P2[6] + 0.003 P2[4] + P2[6] + 0.055 P2[4] P2[4] - P2[6] + 0.086 P2[4] + P2[6] + 0.050 P2[4] P2[4] - P2[6] + 0.054 P2[4] + P2[6] + 0.047 P2[4] P2[4] - P2[6] + 0.057 P2[4] + P2[6] + 0.055 P2[4] P2[4] - P2[6] + 0.042 Document Number: 001-12981 Rev. *J Page 26 of 52 CY8CLED08 Table 6. 3.3-V DC Analog Reference Specifications Reference ARF_CR [5:3] Reference Power Settings Symbol Reference VREFHI RefPower = high Opamp bias = high VAGND VREFLO VREFHI RefPower = high Opamp bias = low 0b010 RefPower = medium Opamp bias = high VAGND VREFLO VREFHI VAGND VREFLO VREFHI RefPower = medium Opamp bias = low All power settings. Not allowed for 3.3 V All power settings. Not allowed for 3.3 V VAGND VREFLO 0b011 0b100 - - VREFHI RefPower = high Opamp bias = high VAGND VREFLO VREFHI RefPower = high Opamp bias = low VAGND VREFLO 0b101 VREFHI RefPower = medium Opamp bias = high VAGND VREFLO VREFHI RefPower = medium Opamp bias = low VAGND VREFLO Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low - - Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low VDD VDD/2 Vss VDD VDD/2 Vss VDD VDD/2 Vss VDD VDD/2 Vss - - P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) Description Min VDD - 0.06 VDD/2 - 0.05 Vss VDD - 0.060 VDD/2 - 0.028 Vss VDD - 0.058 VDD/2 - 0.037 Vss VDD - 0.057 VDD/2 - 0.025 Vss - - P2[4] + 1.213 P2[4] P2[4] - 1.333 P2[4] + 1.217 P2[4] P2[4] - 1.320 P2[4] + 1.217 P2[4] P2[4] - 1.322 P2[4] + 1.219 P2[4] P2[4] - 1.324 Typ VDD - 0.010 Max VDD Unit V V V V V V V V V V V V - - V V V V V V V V V V V V VDD/2 - 0.002 VDD/2 + 0.040 Vss + 0.009 VDD - 0.006 Vss + 0.056 VDD VDD/2 - 0.001 VDD/2 + 0.025 Vss + 0.005 VDD - 0.008 Vss + 0.034 VDD VDD/2 - 0.002 VDD/2 + 0.033 Vss + 0.007 VDD - 0.006 Vss + 0.046 VDD VDD/2 - 0.001 VDD/2 + 0.022 Vss + 0.004 - - P2[4] + 1.291 P2[4] P2[4] - 1.294 P2[4] + 1.294 P2[4] P2[4] - 1.296 P2[4] + 1.294 P2[4] P2[4] - 1.297 P2[4] + 1.295 P2[4] P2[4] - 1.297 Vss + 0.030 - - P2[4] + 1.367 P2[4] P2[4] - 1.208 P2[4] + 1.368 P2[4] P2[4] - 1.261 P2[4] + 1.369 P2[4] P2[4] - 1.262 P2[4] + 1.37 P2[4] P2[4] - 1.262 Document Number: 001-12981 Rev. *J Page 27 of 52 CY8CLED08 Table 6. 3.3-V DC Analog Reference Specifications Reference ARF_CR [5:3] Reference Power Settings RefPower = high Opamp bias = high Symbol Reference VREFHI VAGND VREFLO VREFHI RefPower = high Opamp bias = low 0b110 RefPower = medium Opamp bias = high VAGND VREFLO VREFHI VAGND VREFLO VREFHI RefPower = medium Opamp bias = low 0b111 All power settings. Not allowed for 3.3 V VAGND VREFLO - Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low - Description 2 x Bandgap Bandgap Vss 2 x Bandgap Bandgap Vss 2 x Bandgap Bandgap Vss 2 x Bandgap Bandgap Vss - Min 2.507 1.203 Vss 2.516 1.241 Vss 2.510 1.240 Vss 2.515 1.258 Vss - Typ 2.598 1.307 Vss + 0.012 2.598 1.303 Vss + 0.007 2.599 1.305 Vss + 0.008 2.598 1.302 Vss + 0.005 - Max 2.698 1.424 Vss + 0.067 2.683 1.376 Vss + 0.040 2.693 1.374 Vss + 0.048 2.683 1.355 Vss + 0.03 - Unit V V V V V V V V V V V V - 7.0.2 DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters ar measured to 5 V and 3.3 V at 25 C and are for design guidance only. Table 7-7. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor unit value (continuous time) Capacitor unit value (switched capacitor) Min - - Typ 12.2 80 Max - - Units k fF Notes 7.0.3 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured to 5 V and 3.3 V at 25 C and are for design guidance only. Document Number: 001-12981 Rev. *J Page 28 of 52 CY8CLED08 Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. Table 7-8. DC POR and LVD Specifications Symbol Description Min Typ 2.91 4.39 4.55 Max Units V V V Notes VDD must be greater than or equal to 2.5 V during startup, reset from the XRES pin, or reset from Watchdog. VDD Value for PPOR Trip (positive VPPOR0R ramp) VPPOR1R PORLEV[1:0] = 00b VPPOR2R PORLEV[1:0] = 01b PORLEV[1:0] = 10b VPPOR0 VPPOR1 VPPOR2 VDD Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VDD Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b VDD Value for PUMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b - - - 2.82 4.39 4.55 - V V V VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 - - - 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 92 0 0 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 - - - 2.98[6] 3.08 3.20 4.08 4.57 4.74[7] 4.82 4.91 mV mV mV V V V V V V V V V V V V V V V V V VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 Notes 6. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 7. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. Document Number: 001-12981 Rev. *J Page 29 of 52 CY8CLED08 7.0.4 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 C and are for design guidance only. Table 7-9. DC Programming Specifications Symbol VDDP Description VDD for programming and erase Min 4.5 Typ 5 Max 5.5 Units V Notes This specification applies to the functional requirements of external programmer tools. This specification applies to the functional requirements of external programmer tools. This specification applies to the functional requirements of external programmer tools. This specification applies to this device when it is executing internal flash writes. VDDLV Low VDD for verify 3 3.1 3.2 V VDDHV High VDD for verify 5.1 5.2 5.3 V VDDIWRITE Supply voltage for flash write operation 3.0 - 5.25 V IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Supply current during programming or verify Input low voltage during programming or verify Input high voltage during programming or verify Input current when applying VILP to P1[0] or P1[1] during programming or verify Input current when applying VIHP to P1[0] or P1[1] during programming or verify Output low voltage during programming or verify Output high voltage during programming or verify Flash endurance (per block) Flash endurance (total)[9] Flash data retention - - 2.2 - - - VDD - 1.0 50,000[8] 1,800,000 10 5 - - - - - - - - - 25 0.8 - 0.2 1.5 Vss + 0.75 VDD - - - mA V V mA mA V V - - Years Erase/write cycles per block. Erase/write cycles. Driving internal pull-down resistor. Driving internal pull-down resistor. Notes 8. The 50,000 cycle Flash endurance per block will only be guaranteed if the Flash is operating within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25 V. 9. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information. 10. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO specifications sections.The I2C GPIO pins also meet the above specs. Document Number: 001-12981 Rev. *J Page 30 of 52 CY8CLED08 7.0.5 DC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 C and are for design guidance only. Table 7. DC I2C Specifications Parameter VILI2C[10] VIHI2C[10] Input low level Description Min - - Input high level 0.7 x VDD Typ - - - Max 0.3 x VDD 0.25 x VDD - Units V V V Notes 3.0 V VDD 3.6 V 4.75 V VDD 5.25 V 3.0 V VDD 5.25 V 7.1 AC Electrical Characteristics 7.1.1 AC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 C and are for design guidance only. Table 7-10. AC Chip Level Specifications Symbol FIMO FCPU1 FCPU2 F48M F24M F32K1 F32K_U Description Internal main oscillator frequency CPU frequency (5 V nominal) CPU frequency (3.3 V nominal) Digital PSoC block frequency Digital PSoC block frequency Internal low speed oscillator frequency Internal low speed oscillator untrimmed frequency Min 23.4 0.0914 0.0914 0 0 15 5 Typ 24 24 12 48 24 32 - Max 24.6[11] 24.6[11,12] 12.3[12,13] 49.2[11,12,14] 24.6[12, 14] 64 100 Units MHz MHz MHz MHz MHz kHz kHz Notes Trimmed. Using factory trim values. Trimmed. Using factory trim values. SLIMO mode = 0. Trimmed. Using factory trim values.SLIMO mode = 0. Refer to the AC Digital Block Specifications below. After a reset and before the M8C starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on timing this. Accuracy is capacitor and crystal dependent. 50% duty cycle. Multiple (x732) of crystal frequency. DCILO F32K2 Internal Low Speed Oscillator Duty Cycle External Crystal Oscillator 20 - 50 32.768 80 - % kHz FPLL PLL Frequency - 0.5 0.5 - 23.986 - - 1700 - 10 50 2620 MHz ms ms ms TPLLSLEW PLL Lock Time TPLLSLEWSL PLL Lock Time for Low Gain Setting OW TOS External Crystal Oscillator Startup to 1% Notes 11. 4.75 V < VDD < 5.25 V. 12. Accuracy derived from IMO with appropriate trim for VDD range. 13. 3.0 V < VDD < 3.6 V. 14. See the individual user module data sheets for information on maximum frequencies for user modules. Document Number: 001-12981 Rev. *J Page 31 of 52 CY8CLED08 Table 7-10. AC Chip Level Specifications (continued) Symbol TOSACC Description External crystal oscillator startup to 100 ppm Min - Typ 2800 Max 3800 Units ms Notes The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 mW maximum drive level 32.768 kHz crystal. 3.0V VDD 5.5 V, -40 C TA 85 C. TXRST DC24M Step24M Fout48M FMAX SRPOWER_ UP External reset pulse width 24 MHz duty cycle 24 MHz trim step size 48 MHz output frequency Maximum frequency of signal on row input or row output. Power supply slew rate Time from End of POR to CPU executing code 10 40 - 46.8 - - - - 50 50 48.0 - - 16 - 60 - 49.2[11,13] 12.3 250 100 ms % kHz MHz MHz V/ms ms Trimmed. Utilizing factory trim values. TPOWERUP VDD slew rate during power up. Power up from 0 V. See the System Resets section of the PSoC Technical Reference Manual. N = 32 tjit_IMO[15] 24 MHz IMO cycle-to-cycle jitter (RMS) 24 MHz IMO long term N cycle-to-cycle jitter (RMS) 24 MHz IMO period jitter (RMS) [15] 24 MHz IMO cycle-to-cycle jitter (RMS) tjit_PLL 24 MHz IMO long term N cycle-to-cycle jitter (RMS) 24 MHz IMO period jitter (RMS) - - - - - - 200 300 100 200 300 100 700 900 400 800 1200 700 ps ps N = 32 Figure 7-3. PLL Lock Timing Diagram PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 7-4. PLL Lock for Low Gain Setting Timing Diagram PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Document Number: 001-12981 Rev. *J Page 32 of 52 CY8CLED08 Figure 7-5. External Crystal Oscillator Startup Timing Diagram 32K Select TOS 32 kHz F32K2 7.0.1 AC GPIO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 C and are for design guidance only. Table 7-11. AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO operating frequency Rise time, normal strong mode, Cload = 50 pF Fall time, normal strong mode, Cload = 50 pF Rise time, slow strong mode, Cload = 50 pF Fall time, slow strong mode, Cload = 50 pF Min 0 3 2 10 10 Typ - - - 27 22 Max 12 18 18 - - Units MHz ns ns ns ns Notes Normal strong mode VDD = 4.5 to 5.25 V, 10% - 90% VDD = 4.5 to 5.25 V, 10% - 90% VDD = 3 to 5.25 V, 10% - 90% VDD = 3 to 5.25 V, 10% - 90% Figure 1. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS 7.0.2 AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured to 5 V and 3.3 V at 25 C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3 V. Table 7-12. 5-V AC Operational Amplifier Specifications Symbol TROA Description Rising settling time from 80% of V to 0.1% of V (10 pF load, unity gain) Power = Low, opamp bias = Low Power = Medium, opamp bias = High Power = High, opamp bias = High Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, opamp bias = Low Power = Medium, opamp Bias = High Power = High, opamp bias = High Min Typ Max Units s s s s s s Notes - - - - - - 3.9 0.72 0.62 TSOA - - - - - - 5.9 0.92 0.72 Note 15. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products - AN5054 for more information. Document Number: 001-12981 Rev. *J Page 33 of 52 CY8CLED08 Table 7-12. 5-V AC Operational Amplifier Specifications (continued) Symbol SRROA Description Rising slew rate (20% to 80%)(10 pF load, unity gain) Power = Low, opamp bias = Low Power = Medium, opamp bias = High Power = High, opamp bias = High Falling slew rate (20% to 80%)(10 pF load, unity gain) Power = Low, opamp bias = Low Power = Medium, opamp bias = High Power = High, opamp bias = High Gain bandwidth product Power = Low, opamp bias = Low Power = Medium, opamp bias = High Power = High, opamp bias = High Noise at 1 kHz (Power = Medium, opamp bias = High) Min Typ Max Units Notes 0.15 1.7 6.5 0.01 0.5 4.0 0.75 3.1 5.4 - - - - - - - - - - 100 - - - - - - - - - - V/s V/s V/s V/s V/s V/s MHz MHz MHz nV/rt-Hz SRFOA BWOA ENOA Table 7-13. 3.3-V AC Operational Amplifier Specifications Symbol TROA Description Rising settling time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, opamp bias = Low Power = Low, opamp bias = High Falling settling time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, opamp bias = Low Power = Medium, opamp bias = High Rising slew rate (20% to 80%)(10 pF load, unity gain) Power = Low, opamp bias = Low Power = Medium, opamp bias = High Falling slew rate (20% to 80%)(10 pF load, unity gain) Power = Low, opamp bias = Low Power = Medium, opamp bias = High Gain bandwidth product Power = Low, opamp bias = Low Power = Medium, opamp bias = High Noise at 1 kHz (Power = Medium, opamp bias = High) Min Typ Max Units s s s s Notes - - - - 3.92 0.72 TSOA - - 0.31 2.7 0.24 1.8 0.67 2.8 - - - - - - - - - 100 5.41 0.72 - - - - - - - SRROA V/s V/s V/s V/s MHz MHz nV/rt-Hz SRFOA BWOA ENOA When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Document Number: 001-12981 Rev. *J Page 34 of 52 CY8CLED08 Figure 7-6. Typical AGND Noise with P2[4] Bypass nV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 7-7. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 0.01 0.1 Freq (kHz) 1 10 100 7.4.4 AC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, 3.0 V to 3.6 V and -40 C TA 85 C, or 2.4 V to 3.0 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V at 25 C and are for design guidance only. Table 7-14. AC Low Power Comparator Specifications Symbol TRLPC Description LPC response time Min - Typ - Max 50 Units s Notes 50 mV overdrive comparator reference set within VREFLPC. Document Number: 001-12981 Rev. *J Page 35 of 52 CY8CLED08 7.4.5 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 C and are for design guidance only. Table 8. AC Digital Block Specifications Function Description Min Typ Max Unit Notes All functions Block input clock frequency VDD 4.75 V VDD < 4.75 V - - - - - 50[16] - - - 50[16] 20 50[16] 50[16] - - - - - - - 50[16] - - - - - - - - - - - - - - - - - - - - - 49.2 24.6 49.2 24.6 24.6 - 49.2 24.6 24.6 - - - - 49.2 24.6 49.2 24.6 24.6 8.2 4.1 - MHz MHz MHz MHz MHz ns MHz MHz MHz ns ns ns ns MHz MHz MHz MHz MHz MHz MHz ns The baud rate is equal to the input clock frequency divided by 8. The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. The input clock is the SPI SCLK in SPIS mode. Timer Input clock frequency No capture, VDD 4.75 V No capture, VDD < 4.75 V With capture Capture pulse width Counter Input clock frequency No enable input, VDD 4.75 V No enable input, VDD < 4.75 V With enable input Enable input pulse width Dead Band Kill pulse width Asynchronous restart mode Synchronous restart mode Disable mode Input clock frequency VDD 4.75 V VDD < 4.75 V CRCPRS Input clock frequency (PRS Mode) VDD 4.75 V VDD < 4.75 V CRCPRS Input clock frequency (CRC Mode) SPIM SPIS Input clock frequency Input clock (SCLK) frequency Width of SS_negated between transmissions Transmitter Input clock frequency VDD 4.75 V, 2 stop bits VDD 4.75 V, 1 stop bit VDD < 4.75 V Receiver Input clock frequency VDD 4.75 V, 2 stop bits VDD 4.75 V, 1 stop bit VDD < 4.75 V - - - - - - 49.2 24.6 24.6 MHz MHz MHz The baud rate is equal to the input clock frequency divided by 8. - - - - - - 49.2 24.6 24.6 MHz MHz MHz Note 16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-12981 Rev. *J Page 36 of 52 CY8CLED08 7.4.6 AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 C and are for design guidance only. Table 7-15. 5-V AC Analog Output Buffer Specifications Symbol TROB Description Rising settling time to 0.1%, 1 V Step, 100 pF Load Power = Low Power = High Falling settling time to 0.1%, 1 V Step, 100 pF Load Power = Low Power = High Rising slew rate (20% to 80%), 1 V Step, 100 pF Load Power = Low Power = High Falling slew rate (80% to 20%), 1 V Step, 100 pF Load Power = Low Power = High Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF Load Power = Low Power = High Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF Load Power = Low Power = High Min Typ Max Units s s s s Notes - - - - 0.65 0.65 0.65 0.65 0.8 0.8 300 300 - - - - - - - - - - - - 2.5 2.5 2.2 2.2 - - - - - - - - TSOB SRROB V/s V/s V/s V/s MHz MHz kHz kHz SRFOB BWOB BWOB Table 7-16. 3.3-V AC Analog Output Buffer Specifications Symbol TROB Description Rising settling time to 0.1%, 1 V Step, 100 pF Load Power = Low Power = High Falling settling time to 0.1%, 1 V Step, 100 pF Load Power = Low Power = High Rising slew rate (20% to 80%), 1 V Step, 100 pF Load Power = Low Power = High Falling slew rate (80% to 20%), 1 V Step, 100 pF Load Power = Low Power = High Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF Load Power = Low Power = High Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF Load Power = Low Power = High Min Typ Max Units s s s s Notes - - - - 0.5 0.5 0.5 0.5 0.7 0.7 - - - - - - - - - - 3.8 3.8 2.6 2.6 - - - - - - TSOB SRROB V/s V/s V/s V/s MHz MHz SRFOB BWOB BWOB 200 200 - - - - kHz kHz Note 17. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-12981 Rev. *J Page 37 of 52 CY8CLED08 7.4.7 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 C and are for design guidance only. Table 7-17. 5V AC External Clock Specifications Symbol Description Min Typ Max Units Notes FOSCEXT - - - Frequency High period Low period Power up IMO to switch 0.093 20.6 20.6 150 - - - - 24.6 5300 - - MHz ns ns s Table 7-18. 3.3V AC External Clock Specifications Symbol Description Min Typ Max Units Notes FOSCEXT FOSCEXT - - - Frequency with CPU clock divide by 1[18] 0.093 0.186 41.7 41.7 150 - - - - - 12.3 24.6 5300 - - MHz MHz ns ns s Frequency with CPU clock divide by 2 or greater[19] High period with CPU clock divide by 1 Low period with CPU clock divide by 1 Power up IMO to switch 7.4.8 AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 C and are for design guidance only. Table 7-19. AC Programming Specifications Symbol Description Rise time of SCLK Fall time of SCLK Data setup time to falling edge of SCLK Data hold time from falling edge of SCLK Frequency of SCLK Flash erase time (block) Flash block write time Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Flash erase time (Bulk) Min 1 1 40 40 0 - - - - - Typ - - - - - 10 10 - - 95 Max 20 20 - - 8 - - 45 50 - Units ns ns ns ns MHz ms ms ns ns ms Notes TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TERASEALL TPROGRAM_HOT Flash block erase + flash block write time TPROGRAM_COLD Flash block erase + flash block write time - - - - 80[20] ms 160[20] ms VDD 3.6 3.0 VDD 3.6 Erase all blocks and protection fields at once. 0 C TJ 100 C -40 C TJ 0 C Notes 18. Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 19. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. 20. For the full industrial range, the user must employ a Temperature Sensor User Module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information. Document Number: 001-12981 Rev. *J Page 38 of 52 CY8CLED08 7.4.9 AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 C and are for design guidance only. Table 7-20. AC Characteristics of the I2C SDA and SCL Pins Symbol Standard-Mode Fast-Mode Min Max Min Max SCL clock frequency 0 100 0 400 Hold time (repeated) START condition. After this 4.0 - 0.6 - period, the first clock pulse is generated. LOW period of the SCL clock 4.7 - 1.3 - HIGH period of the SCL clock 4.0 - 0.6 - Setup time for a repeated START condition 4.7 - 0.6 - Data hold time 0 - 0 - Data Setup time 250 - 100[21] - Setup time for STOP condition 4.0 - 0.6 - Bus free time between a STOP and START 4.7 - 1.3 - condition Pulse width of spikes are suppressed by the - - 0 50 input filter. Description Units Notes FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C kHz s s s s s ns s s ns Figure 7-8. Definition for Timing for Fast-/Standard-Mode on the I2C Bus I2C_SDA TSUDATI2C THDSTAI2C I2C_SCL TSPI2C THDDATI2CTSUSTAI2C TBUFI2C THIGHI2C TLOWI2C S START Condition Sr Repeated START Condition TSUSTOI2C P STOP Condition S Note 21. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-12981 Rev. *J Page 39 of 52 CY8CLED08 8. Packaging Information This section illustrates the packaging specifications for the CY8CLED08 EZ-Color device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com. 8.1 Packaging Dimensions Figure 8-1. 48-Pin (7 x 7 x 1.0 mm) QFN (Sawn) SOLDERABLE EXPOSED PAD 001-13191 *E Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com. Pinned vias for thermal conduction are not required for the low-power device. Document Number: 001-12981 Rev. *J Page 40 of 52 CY8CLED08 8.1 Thermal Impedances Table 8-1. Thermal Impedances per Package Package Typical JA[22] 48-pin QFN[23] 18 C/W 8.2 Capacitance on Crystal Pins Table 8-2. Typical Package Capacitance on Crystal Pins Package Package Capacitance 48-pin QFN 2.3 pF 8.3 Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 8-3. Solder Reflow Peak Temperature Package Maximum Peak Temperature Time at Maximum Peak Temperature 48-pin QFN 260 C 30 s Notes 22. TJ = TA + POWER x JA 23. To achieve the thermal impedance specified for the QFN package, refer to Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com. Document Number: 001-12981 Rev. *J Page 41 of 52 CY8CLED08 9. Development Tool Selection This section presents the development tools available for all current PSoC based devices including the CY8CLED08 EZ-Color family. 9.3 Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store. 9.3.1 CY3210-MiniProg1 9.1 Software Tools 9.1.1 PSoC Designer At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com and includes a free C compiler. 9.1.2 PSoC Programmer The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube in-circuit emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com. 9.2 Hardware Tools 9.2.1 In-Circuit Emulator 9.3.2 CY3210-PSoCEval1 A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of the USB port. The base unit is universal and will operate with all PSoC based devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. 9.2.2 I2C to USB Bridge The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable The I2C to USB Bridge is a quick and easy link from any design or application's I2C bus to a PC via USB for design testing, debugging and communication. Document Number: 001-12981 Rev. *J Page 42 of 52 CY8CLED08 9.4 Device Programmers All device programmers are sold at the Cypress Online Store. 9.4.1 CY3216 Modular Programmer USB 2.0 Cable 9.4.2 CY3207ISSP In-System Serial Programmer (ISSP) The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: Modular Programmer Base 3 Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable 9.5 Accessories (Emulation and Programming) Table 9. Emulation and Programming Accessories Part # Pin Package Flex-Pod Kit[24] Foot Kit[25] Adapter[26] CY8CLED08-48LTXI 48-pin QFN CY3250-LED08QFN CY3250-48QFN-FK Adapters can be found at http://www.emulation.com. Notes 24. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 25. Foot kit includes surface mount feet that can be soldered to the target PCB. 26. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. Document Number: 001-12981 Rev. *J Page 43 of 52 CY8CLED08 10. Ordering Information 10.1 Key Device Features The following table lists the CY8CLED08 EZ-Color devices' key package features and ordering codes. Table 10. Device Key Features and Ordering Information Analog Blocks (Columns of 3) Digital Blocks (Rows of 4) Switch Mode Pump Temperature Range Digital I/O Pins XRES Pin Package Ordering Code 48-pin (7 x 7) QFN (Sawn) CY8CLED08-48LTXI 48-pin (7 x 7) QFN (Tape and Reel) (Sawn) CY8CLED08-48LTXIT 16 K 16 K 256 256 Yes Yes -40 C to +85 C 8 -40 C to +85 C 8 12 12 44 44 12 12 4 4 Analog Outputs Flash (Bytes) RAM (Bytes) Analog Inputs Yes Yes 10.2 Ordering Code Definitions CY 8 C LED xx - xx xxxx Package Type: LTX = QFN Pb-free Pin Count Part Number LED Family Code Thermal Rating: I = Industrial Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Document Number: 001-12981 Rev. *J Page 44 of 52 CY8CLED08 11. Acronyms Table 11-1 lists the acronyms that are used in this document. Table 11-1. Acronyms Used in this Datasheet Acronym Description Acronym Description AC ADC API CMOS CPU CRC CT DAC DC DTMF ECO EEPROM GPIO I/O ICE IDE ILO IMO IrDA ISSP LCD LED LPC LVD alternating current analog-to-digital converter application programming interface complementary metal oxide semiconductor central processing unit cyclic redundancy check continuous time digital-to-analog converter direct current dual-tone multi-frequency external crystal oscillator electrically erasable programmable read-only memory general purpose I/O input/output in-circuit emulator integrated development environment internal low speed oscillator internal main oscillator infrared data association in-system serial programming liquid crystal display light-emitting diode low power comparator low-voltage detect MAC MIPS PCB PDIP PLL POR PPOR PRS PSoC(R) PWM QFN RTC SAR SROM SC SMP SPI SRAM SSOP UART USB WDT XRES multiply-accumulate million instructions per second printed circuit board plastic dual-in-line package phase-locked loop power-on reset precision power on reset pseudo-random sequence Programmable System-on-Chip pulse-width modulator quad flat no leads real time clock successive approximation supervisory read only memory switched capacitor switch mode pump serial peripheral interface static random access memory shrink small-outline package universal asynchronous receiver / transmitter universal serial bus watchdog timer external reset 12. Reference Documents Design Aids - Reading and Writing PSoC(R) Flash - AN2015 (001-40459) Understanding Datasheet Jitter Specifications for Cypress Timing Products - AN5054 (001-14503) Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages - available at http://www.amkor.com. Document Number: 001-12981 Rev. *J Page 45 of 52 CY8CLED08 13. Document Conventions 13.1 Units of Measure Table 13-1 lists the units of measure. Table 13-1. Units of Measure Symbol dB oC fF pF kHz MHz rt-Hz k A mA nA pA F H Unit of Measure Symbol s ms ns ps V mV mVpp nV V W W mm ppm % Unit of Measure microseconds milliseconds nanoseconds picoseconds microvolts millivolts millivolts peak-to-peak nanovolts volts microwatts watts millimeter parts per million percent decibels degree Celsius femtofarads picofarads kilohertz megahertz root hertz kilohms microamperes milliamperes nanoamperes pikoamperes microfarads microhenry 13.2 Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal. 14. Glossary active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. The basic programmable opamp circuits. These are switched capacitor (SC) and continuous time (CT) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. analog blocks analog-to-digital (ADC) Application programming interface (API) asynchronous Bandgap reference bandwidth Document Number: 001-12981 Rev. *J Page 46 of 52 CY8CLED08 14. Glossary (continued) bias 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. A program that translates a high level language, such as C, into machine language. In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to `1'. block buffer bus clock comparator compiler configuration space crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear check (CRC) feedback shift register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. A period of time when neither of two or more signals are in their active state or in transition. The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. debugger dead band digital blocks Document Number: 001-12981 Rev. *J Page 47 of 52 CY8CLED08 14. Glossary (continued) digital-to-analog (DAC) duty cycle emulator A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation. The relationship of a clock period high time to its low time, expressed as a percent. Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is OFF. The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. The number of cycles or events per unit of time, for a periodic function. The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). External Reset (XRES) Flash Flash block frequency gain I2C ICE input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. interrupt service routine (ISR) jitter low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold. (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. Document Number: 001-12981 Rev. *J Page 48 of 52 CY8CLED08 14. Glossary (continued) master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. The reference to a circuit containing both analog and digital techniques and components. A device that imposes a signal on a carrier. 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. A circuit that may be crystal controlled and is used to generate a clock frequency. A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. A group of pins, usually eight. A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of hardware reset. Cypress Semiconductor's PSoC(R) is a registered trademark and Programmable System-on-ChipTM is a trademark of Cypress. microcontroller mixed-signal modulator noise oscillator parity Phase-locked loop (PLL) pinouts port Power-on reset (POR) PSoC(R) PSoC DesignerTM The software for Cypress' Programmable System-on-Chip technology. pulse-width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. A storage device with a specific capacity, such as a bit or byte. A means of bringing a system back to a know state. See hardware reset and software reset. An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. register reset ROM Document Number: 001-12981 Rev. *J Page 49 of 52 CY8CLED08 14. Glossary (continued) serial 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. The time it takes for an output signal or value to stabilize after the input has changed from one value to another. A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. A signal following a character or block that prepares the receiving device to receive the next character or block. 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level Application Programming Interface (API) for the peripheral function. The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V. A name for a power net meaning "voltage source." The most negative power supply signal. A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. settling time shift register slave device SRAM SROM stop bit synchronous tri-state UART user modules user space VDD VSS watchdog timer Document Number: 001-12981 Rev. *J Page 50 of 52 CY8CLED08 15. Document History Page Document Title: CY8CLED08 EZ-ColorTM HB LED Controller Document Number: 001-12981 Revision ECN Orig. of Change Submission Date Description of Change ** *A *B *C 1148504 SFVTMP3 1391163 2763950 2794355 AESA DPT XBM 06/13/2007 See ECN 10/01/0209 10/28/2009 New document (revision **). Added 28 pin SSOP Added 48QFN package diagram (Sawn) Saw Marketing part number in ordering information. Added "Contents" on page 3 Updated "Development Tools" on page 7. Corrected FCPU1 and FCPU2 parameters in "AC Chip Level Specifications" on page 31. Corrected package diagram for 28-Pin (210-Mil) SSOP (Figure 8-1.) Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as follows: Replaced TRAMP (time) with SRPOWER_UP (slew rate) specification. Added note to Flash Endurance specification. Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, TPROGRAM_HOT, and TPROGRAM_COLD specifications. Corrected the Pod Kit part numbers. Updated Development Tool Selection. Updated copyright and Sales, Solutions, and Legal Information URLs. Updated 28-Pin (210-Mil) SSOP package diagram. Updated ordering information table. Removed part numbers CY8CLED08-48LFXI and CY8CLED08-48LFXIT Updated copyright section. Updated package diagram for spec 51-85061 Updated Cypress website links Added TBAKETEMP and TBAKETIME parameters Removed sections "Third Party Tools" and "Build a PSoC Emulator" Removed obsolete parts. Added DC I2C Specifications table. Added F32K_U max limit. Added Tjit_IMO specification, removed existing jitter specifications. Updated DC Analog reference, DC Analog output buffer specifications and DC operational amplifier specifications tables. Updated Units of Measure, Acronyms, Glossary, and References sections. Updated solder reflow specifications. No specific changes were made to AC Digital Block Specifications table and I2C Timing Diagram. They were updated for clearer understanding. Updated Figure 6-6 as the labelling for y-axis was incorrect. Template and styles update. Updated Getting Started, Development Tools, and Designing with PSoC Designer. Removed obsolete kits. Removed references to 48-pin SSOP and 28-pin SSOP. *D *E 2819954 2850593 CGX FRE 12/02/2009 01/14/2010 *F 2896238 CGX 03/19/10 *G 2903043 NJF 04/01/2010 *H *I 3053097 3114945 CGX NJF 10/08/2010 12/19/10 *J 3284963 DIVA 07/08/11 Document Number: 001-12981 Rev. *J Page 51 of 52 CY8CLED08 16. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 16.1 Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless 16.2 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 (c) Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-12981 Rev. *J Revised July 8, 2011 Page 52 of 52 PSoC DesignerTM and EZ-ColorTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All other products and company names mentioned in this document may be the trademarks of their respective holders. |
Price & Availability of CY8CLED02
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |